1. Field of the Invention
The present invention generally relates to mesh model creating methods, simulation apparatuses and computer-readable storage media, and more particularly to a mesh model creating method for creating a mesh model that is used to carry out an electrical simulation of a printed circuit and the like, to a simulation apparatus that uses the mesh model created by such a mesh model creating method, and to a computer-readable storage medium that stores a program for causing a computer to create the mesh model by such a mesh model creating method and/or to carry out an electrical simulation using such a mesh model.
2. Description of the Related Art
When carrying out an electrical simulation of a printed circuit and the like, a technique that is often used creates a mesh model by dividing a power supply layer and a ground layer of the printed circuit into a plurality of meshes, and assigning inductance (L), capacitance (C) and resistance (R) to each mesh. When analyzing the mesh model in which the entire printed circuit is divided into the plurality of meshes, the analyzing time increases if the meshes are made smaller to improve the analyzing accuracy, and the analyzing accuracy deteriorates if the meshes are made larger to reduce the analyzing time.
In the conventional simulation methods, the mesh model is creased by dividing a region that is a target of the simulation into a plurality of square meshes, and assigning a constant sheet inductance value (L value) and a sheet resistance value (R value) to each mesh. However, particularly in a case where the region that is the target of the simulation has a complex shape, it is necessary to divide the region into extremely small meshes, as shown in FIG. 1. FIG. 1 is a diagram showing an example of the division of the region into the meshes according to the conventional simulation method.
A Japanese Laid-Open Patent Application No. 10-289332 proposes a method of redividing meshes in small steps when carrying out the simulation. In addition, a Japanese Laid-Open Patent Application No. 2001-237412 proposes a method of reducing a number of nodes on a substrate surface, when treating a substrate as an aggregate of unit cell models that are models of mutual connections of resistors, by making the dimensions of the unit cell models variable and connecting the unit cell models having different sizes by an appropriate connection model. Furthermore, a Japanese Laid-Open Patent Application No. 2002-288241 proposes a method of extracting surface data of a metal housing from three-dimensional data of an electrical circuit device, dividing the surfaces corresponding to the surface data into rectangular meshes, and outputting mesh division data to an electromagnetic field intensity computation apparatus.
According to the conventional simulation method, if the region that is the target of the simulation has a complex shape, it is necessary to divide the target region into extremely small meshes, as shown in FIG. 1. But although the analyzing accuracy improves when the meshes are extremely small, there was a problem in that the analyzing time becomes long. On the other hand, when the meshes are made larger so as to reduce the analyzing time, there was a problem in that the analyzing accuracy greatly deteriorates.